This invention relates to a semiconductor device in which a plurality of field effect transistors (FET's) such as complementary metal oxide semiconductor (CMOS) transistors are formed on an insulating substrate.
As a semiconductor device of this type, a semiconductor device of an SOS (silicon on sapphire) structure is known in which a CMOS transistor having a gate formed of a polycrystalline silicon (poly-Si) is formed on a sapphire substrate.
The manufacture of a conventional semiconductor device of an SOS structure will be explained by referring to FIG. 1.
An SOS wafer is prepared in which a silicon film 2 is epitaxially grown in thickness of 0.8 .mu.m on a (1102) sapphire substrate. Usually, an SOS wafer not doped with any impurity has a P-type silicon film of a higher resistance (a specific resistance of above 100 .OMEGA..multidot.cm). Silicon film 2 of the SOS wafer is selectively removed by a normal photoengraving process (PEP) to provide islands (FIG. 1(a)). After formation of these islands, a CVD (Chemical Vapor Deposition).multidot.SiO.sub.2 film 3 which is used as a mask during a selective etching is removed and a gate oxide film 4 and a poly-Si 5 constituting a gate electrode are sequentially grown on the resultant structure (FIG. 1(b)). A gate region 11 is selectively formed by a PEP technique (FIG. 1(c)). A PSG (phosphosilicate glass) film 6 is deposited on the whole surface of the resultant structure and selectively removed to leave a region below which an n-channel transistor is formed. The wafer is heat-treated at a high temperature in a diffusion furnace maintained in a boron (B) atmosphere. By so doing, phosphorus is diffused below the PSG film 6 to provide an n.sup.+ region 7 and boron is diffused in the PSG layer-free area to provide a p.sup.+ region 8 (FIG. 1(d)). Then, a CVD.multidot.SiO.sub.2 film 9 is deposited on the surface of the resultant structure and selectively apertured to provide an electrode takeout opening. Then, aluminium 10 is evaporated on the resultant structure and an electrode connection is subjected to a patterning process to provide a C-MOS comprising a p-channel MOS and an n-channel MOS (FIG. 1(e)).
In order to attain a higher integration density of elements, a poly-Si constituting a gate electrode is processed to obtain a single electroconductivity type in the CMOS semiconductor device. In the above-mentioned manufacturing process, however, a poly-Si gate of an n.sup.+ electroconductivity type and poly-Si gate of a p.sup.+ electroconductivity type co-exist and a metal, such as aluminium, has to be deposited in a connected area between the n.sup.+ and p.sup.+ electroconductive poly-Si gates, preventing a higher integration density.
The manufacturing process of a CMOS having transistors of a single electroconductivity type is as follows:
After completion of the above-mentioned step (FIG. 1(b)) a PSG film 12 is deposited on the surface of the resultant structure and phosphorus is diffused at a high temperature into a poly-Si film (FIG. 1(b')). Then, after a PSG film 12 is removed, a CVD.multidot.SiO.sub.2 film 13 is deposited and a gate region 11' having an n-type poly-Si film 5 is formed by PEP (FIG. 1(c')). The subsequent steps are the same as those of the abovementioned process. A CVD.multidot.SiO.sub.2 film 13 on the poly-Si film prevents the intrusion of the other impurities in the subsequent steps.
The threshold voltage (V.sub.T) of a CMOS transistor (hereinafter referred to as a CMOS/SOS) formed in the p-type silicon film on the sapphire substrate is expressed by the following equations.
Since the gate voltage of the n-channel transistor when an inversion layer is formed below the gate becomes a threshold voltage (V.sub.Tn), when the width of a maximum depletion layer, xdmax, is smaller than the thickness (t.sub.film) of the silicon film, that is, when ##EQU1## where EQU Q.sub.B =[2N.sub.A q.sub..epsilon.Si (2.phi..sub.t)].sup.1/2( 2)
when ##EQU2##
Since the p-channel transistor acts as a deep depletion type transistor the gate voltage when a depletion layer below a gate reaches the sapphire substrate becomes a threshold voltage (V.sub.Tp) i.e. ##EQU3## where .phi..sub.MS : a work function between a metal and a semiconductor
Q.sub.SS : an amount of positive charges in the gate oxide film PA1 C.sub.OX : a gate capacity PA1 N.sub.A : an acceptor concentration in the silicon film PA1 .epsilon..sub.Si : a dielectric constant of silicon PA1 .phi..sub.t : a Fermi potential
where an Si gate CMOS/SOS comprising n- and p-channel transistors having gates of an n.sup.+ type electroconductivity type is manufactured on the SOS wafer not doped with any impurity, the threshold voltages EQU V.sub.Tn =+0.1(V) EQU V.sub.Tp =-1.2(V)
are obtained. In a large scale integrated circuit etc. the threshold voltages V.sub.Tn =+0.6.about.0.8(V) and V.sub.Tp =-0.6.about.0.8(V) are often required. The above-mentioned threshold voltage V.sub.T has to be obtained by some other method (for example, a method for injecting an ion into a channel below the gate). As seen from Equations (1) to (4) the threshold voltage V.sub.Tp of the p-channel transistor can be made lower by making the acceptor concentration in the silicon film higher and the threshold voltage V.sub.Tn of the n-channel transistor can be also made higher by making the acceptor concentration in the silicon film higher. FIG. 2 shows a gate voltage (V.sub.g) vs. drain (I.sub.D) characteristic. Since, however, the p-channel transistor acts as a deep depletion type transistor a drain leak current (I.sub.DD) is increased by increasing the concentration of the acceptor in the silicon film. An increase in the drain leak current I.sub.DD disadvantageously increases a dissipation power at the stand-by time. The increase in the drain leak current may be controlled by making the silicon film thinner without appreciably increasing the acceptor concentration in the silicon film.
In FIG. 2 the solid lines A.sub.n, A.sub.p substantially show the gate voltage (V.sub.g)-drain current (I.sub.D) characteristic of n- and p-channel transistors of a CMOS construction whose silicon film is not doped with any impurity, and the dotted lines B.sub.n, B.sub.p show the variation of the characteristic of the n- and p-channel transistors when the acceptor concentration N.sub.A in the silicon film is increased (the n-channel transistor is further shifted toward a deeper V.sub.th and the p-channel transistor is further shifted toward a shallower V.sub.th) and the variation of the characteristic (B.sub.p') of the p-channel transistor when the silicon film is made thinner.